Association for Computing Machinery
To handle the demand for very large main memory, the authors are likely to use Non-Volatile Memory (NVM) as main memory. NVM main memory will have higher latency than DRAM. To cope with this, they advocate a less-deep cache hierarchy based on a large last-level, NVM cache. They develop a model that estimates average memory access time and power of a cache hierarchy. The model is based on captured application behavior, an analytical power and performance model, and circuit-level memory models such as CACTI and NVSim. They use the model to explore the cache hierarchy design space and present latency-power tradeoffs for memory intensive SPEC benchmarks and scientific applications.