Exploring Pausible Clocking Based GALS Design for 40-nm System Integration

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Provided by: European Design and Automation Association
Topic: Hardware
Format: PDF
Globally Asynchronous Locally Synchronous (GALS) design has attracted intensive research attention during the last decade. Among the existing GALS design solutions, the pausible clocking scheme presents an elegant solution to address the cross-clock synchronization issues with low hardware overhead. This paper explored the applications of pausible clocking scheme for area/power efficient GALS design. To alleviate the challenge of timing convergence at the system level, area and power balanced system partitioning was applied for GALS design.
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