Exploring the Memory Hierarchy for Packet Processing Applications

Provided by: Academy & Industry Research Collaboration Center
Topic: Mobility
Format: PDF
In the future, network processors must process more computation-intensive network applications and internet traffic and packet-processing tasks become heavier and sophisticated. Since the processor performance is severely related to the average memory access delay and also the number of processor registers affects the performance, cache and register file are two major parts in designing embedded processor architecture. Although increasing cache and register file size leads to performance improvement in packet processing tasks in high traffic networks with too much packets, the increased area, power consumption and memory hierarchy delay are the overheads of these techniques.

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