FABSYN: Floorplan-Aware Bus Architecture Synthesis

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Provided by: Institute of Electrical & Electronic Engineers
Topic: Hardware
Format: PDF
As System-on-Chip (SoC) designs become more complex, it is becoming harder to design communication architectures to handle the ever increasing volumes of inter-component communication. Manual traversal of the vast communication design space to synthesize a communication architecture that meets performance requirements becomes infeasible. In this paper, the authors address this problem by proposing an automated approach for Floorplan-Aware Bus architecture SYNthesis (FABSYN) to synthesize cost-effective, bus-based communication architectures that satisfy the performance constraints in a design.
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