Association for Computing Machinery
With growing system complexity and ever increasing software content, the development of embedded software for upcoming MPSoC architectures is a tremendous challenge. Traditional ISS-based validation becomes infeasible due to the large complexity. Addressing the need for flexible and fast simulating models, the authors introduce in this paper, their approach of abstract processor modeling in the context of multi-processor architectures. They combine modeling of computation on processors with an abstract RTOS and accurate interrupt handling into a versatile, multi-faceted processor model with several levels of features.