International Journal of Innovative Research in Electrical, Electronics, Instrumentation and Control Engineering (IJIREEICE)
The DCT in two dimensions is the core of the JPEG compression. Image and video compression is one of the major components used in video - telephony, videoconferencing and multimedia - related applications. In this paper, the authors describe the design and implementation of a fully pipelined architecture for implementing the JPEG image compression standard. The architecture exploits the principles of pipelining and parallelism in order to obtain high speed and throughput. This design aimed to be implemented in Spartan-3E X C3S500E FPGA.