Fast Multi Operand Decimal Adders Using Digit Compressors with Decimal Carry Generation
The authors consider multi operand decimal adders designed with an architecture implementing first the addition of all the digits of each column (i.e. with the same decimal weight) and then combining in various ways such column sums for obtaining the final result. Different and efficient architectures can be conceived on the basis of compressors of a number of digits (e.g. three) generating a smaller number of digits (e.g. two) and, simultaneously, a decimal carry to be accounted for by the next (to the left) column.