Provided by: Katholieke Universiteit Leuven
Date Added: Jun 2009
The authors present a bit-sliced implementation of AES encryption in counter mode for 64-bit Intel processors. Running at 7.59 cycles/byte on a core 2, it is up to 25% faster than previous implementations, while simultaneously offering protection against timing attacks. In particular, it is the only cache-timing-attack resistant implementation offering competitive speeds for stream as well as for packet encryption: for 576-byte packets, they improve performance over previous bit-sliced implementations by more than a factor of 2.