FASTLANE: Improving Performance of Software Transactional Memory for Low Thread Counts

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Provided by: Association for Computing Machinery
Topic: Storage
Format: PDF
Software Transactional Memory (STM) can lead to scalable implementations of concurrent programs, as the relative performance of an application increases with the number of threads that support it. However, the absolute performance is typically impaired by the overheads of transaction management and instrumented accesses to shared memory. This often leads STM-based programs with low thread counts to perform worse than a sequential, non-instrumented version of the same application. In this paper, the authors propose FASTLANE, a new STM algorithm that bridges the performance gap between sequential execution and classical STM algorithms when running on few cores. FASTLANE seeks to reduce instrumentation costs and thus performance degradation in its target operation range.
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