Fault Reduction in Nonoscale VLSI Interconnection by Using Carbon Nanotubes Technology

Provided by: Science Publishing Group
Topic: Hardware
Format: PDF
As the VLSI technology scales down, significant challenges are facing the fabrication, modeling and performance of the integrated circuits. One of the major challenges for the continuation of the Moore's law is "Interconnects" at Nano-scale. Interconnects become as important as transistors in the current technologies and will dominate the chip performance at the future technologies. Beside their electrical performance, their mechanical performance will be important at the Nano-scale. Wires should be resilient enough to cope with Back-End-Of-Line (BEOL) processes.

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