Fault Tolerance in Network-on-Chip by Using Single Error Correction and Double Error Detection
The emerging technique for communication with in a large VLSI system is a network-on-chip. The fast scaling of technique there has been susceptible faults in the component of the network on chip, thus there is a requirement for technique to maintain circuit reliability. A fault-tolerant NOC (Network-On-Chip) should be having the capacity to detect a fault and recover the system to correctly operate and work according to the mapped application. The paper performed here emphasizes on the learning and assessing of methods for growing flexibility of system interfaces with NOC based Multi-Processor System-On-Chip (MPSOC) design.