International Journal of Advanced Engineering Science and Information Technology (IJAESIT)
In this paper, a new enhanced Lockstep scheme built using a pair of Micro blaze cores is proposed and implemented on Xilinx Virtex-6 FPGA. Lockstep scheme allows detecting and eliminating its internal temporary configuration upsets without interrupting normal functioning. Faults are detected and eliminated using a configuration engine built on the basis of the picoblaze core which, to avoid a single point of failure, is implemented as fault tolerant using triple modular redundancy. The new enhanced lockstep scheme requires significantly shorter error recovery time compared to conventional lockstep scheme and uses significantly smaller number of slices compared to known TMR based design.