Fault Tolerant Delay Insensitive Inter-Chip Communication

Provided by: Institute of Electrical & Electronic Engineers
Topic: Hardware
Format: PDF
Asynchronous interconnect is a promising technology for communication systems. Delay Insensitive (DI) interconnects eliminates relative timing assumptions, offering a robust and flexible approach to on- and inter-chip communication. In the SpiNNaker system - a massively parallel computation platform -a DI system-wide communication infrastructure is employed which uses a 4-phase 3-of-6 code for on-chip communication and a 2-phase 2-of-7 code for inter-chip communication. Fault-tolerance has been evaluated by randomly injecting transient glitches into the off-chip wires. Fault simulation reveals that deadlock may occur in either the transmitter or the receiver as handshake protocols are disrupted.

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