Fault-Tolerant Network Interface for Spatial Division Multiplexing Based Network-on-Chip

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Provided by: National University of Singapore
Topic: Hardware
Format: PDF
The progressive maturity of VLSI manufacturing technology is helping in integrating more and more processing elements and memory units on a single die to form a Multi-Processor System-On-Chip (MPSoC). Network-on-Chip (NoC) is adopted as communication backbone for most of these modern day multiprocessor systems. As complexity of these system scales, there has been a growing concern on the dependability of these processing and communication elements. In this paper, the authors propose a centralized hardware fault-tolerant Network Interface (NI) for NoCs based on spatial division multiplexing.
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