International Journal of Research in Electronics and Computer Engineering (IJRECE)
In this paper, the authors present mechanism to design and implement soft processor on FPGAs. Error-correcting code technique is used, which harden the fault tolerance of soft processors. FPGAs suffer from highly susceptible radiation induced faults example single error upsets. Memories of FPGAs are more susceptible to these faults. Error-correcting code technique is demonstrated in implementation of a fault tolerant soft processor on Xilinx FPGAs. In additional, they used look-ahead technique to synchronize Error-Correcting Code-protected Block Read Access Memory (ECC BRAM) with the soft processor.