Fingerprinting Across On-Chip Memory Interconnects

Provided by: Carnegie Mellon University
Topic: Hardware
Format: PDF
Pairs of cores in a Chip Multi-Processor (CMP) can execute programs redundantly to detect and recover from soft errors. Prior work assumes dedicated cross-core buses to compare the redundant cores' outputs for error detection. In this paper, the authors investigate using the CMP's existing on-chip memory interconnect for comparing hashes of architectural state updates, called fingerprints, across redundant cores. They show that the memory system can support periodic fingerprint comparison. Furthermore, their simulation-based results show that for reasonable comparison intervals, the added load does not affect memory access latency and matches the performance of a dedicated comparison bus.

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