Fixed-Priority Scheduling for Reducing Both the Dynamic and Leakage Energy on Variable Voltage Processors

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Provided by: University of South Australia
Topic: Hardware
Format: PDF
With ever-scaling VLSI technology, the leakage is increasingly becoming a serious concern when addressing the power consumption problem for next-generation real-time embedded systems. Dynamic Voltage Scaling (DVS) is efficient in reducing the dynamic energy consumption of a CMOS processor. However, methods that employ DVS without considering the leakage current are quickly becoming less effective to reduce the processor's overall energy consumption. To be overall energy efficient, the processor may have to run at a higher-than-necessary speed, which will cause a large number of idle intervals.
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