Association for Computing Machinery
The authors propose an architecture that uses NAND flash memory to reduce main memory power in web server platforms. Their architecture uses a two level file buffer cache composed of a relatively small DRAM, which includes a primary file buffer cache, and a flash memory secondary file buffer cache. Compared to a conventional DRAM-only architecture, their architecture consumes orders of magnitude less idle power while remaining cost effective. This is a result of using flash memory, which consumes orders of magnitude less idle power than DRAM and is twice as dense. The client request behavior in web servers, allows them to show that the primary drawbacks of flash memory - endurance and long write latencies - can easily be overcome.