FLEXclusion: Balancing Cache Capacity and On-Chip Bandwidth Via Flexible Exclusion

Provided by: Georgia Institute of Technology
Topic: Hardware
Format: PDF
Exclusive Last-Level Caches (LLCs) reduce memory accesses by effectively utilizing cache capacity. However, they require excessive on-chip bandwidth to support frequent insertions of cache lines on eviction from upper-level caches. Non-inclusive caches, on the other hand, have the advantage of using the on-chip bandwidth more effectively but suffer from a higher miss rate. Traditionally, the decision to use the cache as exclusive or non-inclusive is made at design time. However, the best option for a cache organization depends on application characteristics, such as working set size and the amount of traffic consumed by LLC insertions.

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