Floorplanning and Topology Generation for Application-Specific Network-on-Chip

Network-on-Chip (NoC) architectures have been proposed as a promising alternative to classical bus-based communication architectures. In this paper, the authors propose a two phase's framework to solve application-specific NoCs topology generation problem. At floor-planning phase, they carry out partition driven floor-planning. At post-floor-planning phase, a heuristic method and a min-cost max-flow algorithm is used to insert switches and network interfaces. Finally, they allocate paths to minimize power consumption. The experimental results show their algorithm is effective for power saving.