Floorplanning Exploration and Performance Evaluation of a New Network-on-Chip

Provided by: edaa
Topic: Hardware
Format: PDF
The Network-on-Chip (NoC) paradigm has emerged as a revolutionary methodology in current System-on-Chips (SoCs) for integrating a large number of processing elements in a single die. It has the advantage of enhanced performance, scalability and modularity, compared with previous bus-based communication architectures. Recently, a new Triplet-based Hierarchical Interconnection Network (THIN) has been proposed. In this paper, the authors explore the Three-Dimensional (3D) floorplanning of THIN and present two different floorplanning and routing methods using both the Manhattan routing and the Y-architecture routing architectures.

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