Multi-Processor Systems-on-Chip (MPSoC) designs integrate several processing and memory cores on a single die. To gain performance the trend is to increase the number of cores and parallelism. To manage the complexity of modern MPSoCs, a popular approach is platform based design. Networks-on-Chips (NoC) are emerging as a promising interconnect solution for efficient Multi-Processor System-on-Chips (MPSoCs). The authors propose a methodology that supports the specification of parametric NoCs. They provide sufficient constraints that ensure deadlock-free routing, functional correctness, and liveness of the design. To illustrate their method, they discharge these constraints for a parametric NoC inspired by the HERMES architecture.