Formal Verification of a Pervasive Interconnect Bus System in a High-Performance Microprocessor

Provided by: edaa
Topic: Hardware
Format: PDF
In the people high-performance PowerPC processor, the correctness of the so-called the pervasive interconnect bus system, which provides, among others, test and debug access via external interfaces like JTAG, is of utmost importance. In this paper, they describe their approach in formally verifying the correctness of this bus system to combat the coverage problem of simulation-based techniques. The bus system and the associated arbitration logic support several functionalities such as deadlock detection and the resolution.

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