Institute of Electrical & Electronic Engineers
Quasi delay insensitive asynchronous logic is a very robust system allowing safe implementations while requiring minimal timing assumptions. Unfortunately the design methodologies using this system have always yielded very slow designs. Early output logic is a method which aims to improve the performance of QDI circuits without decreasing their robustness. In order to force QDI restrictions on early output circuits a form of guarding is necessary. This paper presents a new form of guarding which allows partial stage completion allowing desynchronisation of inputs.