Viterbi decoder is employed in wireless communication to decode the convolution codes; those codes are used in or every robust digital communication system. Convolution encoding and Viterbi decoding is a powerful method f or error correction this paper deals with synthesis ands and implementation of Viterbi decoder with a constraint length three and code rate 1/2 and 1/3 in FPGA (Field Programmable Gate Array). The performance of Viterbi decoder in terms of recourses utilization. The design of Viterbi decoder is simulated using Verilog HDL. It synthesized and implementation using Xilix8.2 lies and spartanXC3S400Kit.