Institute of Electrical & Electronic Engineers
In this paper the authors concerned with the application of geometric programming to the design of homogeneous FPGA architectures. The paper builds on an increasing body of work concerned with modeling reconfigurable architectures, and presents a full area and delay model of an FPGA. The authors use a geometric programming framework to show how transistor sizing and high-level architecture parameter selection can now be solved as a concurrent optimization problem. They validate the model through the use of SPICE models and the VPR FPGA architecture simulation tool.