FPGA Based Hardware Implementation of Encryption Algorithm
Reprogrammable devices such as Field Programmable Gate Arrays (FPGA) are used for hardware implementations of cryptographic algorithm. This paper presents an FPGA based Hardware implementation of Advanced Encryption Standard (AES) with 128-bit key as a constant which is used for encrypting the text file and image for secure transmission. Timing report for the files are taken and conclude that text file of 128 bit size is taking less time to encrypt and decrypt compare to the image file. Synthesizing and implementation (translate, map and place and route) of the VERILOG code is carried out on Xilinx - project navigator ISE 12.3 software.