In this paper, the authors describe an efficient hardware realization of the Advanced Encryption Standard (AES) algorithm using FPGA. The AES also known as the Rijndael algorithm was selected as a Standard on October 2, 2000 by National Institute of Standards and Technology (NIST). Encryption algorithms are used to ensure security of transmission channels. They use AES 128- bit block size and 128-bit cipher key for the implementation on Xilinx Virtex 5 FPGA. Xilinx ISETM 12.4 design tool is used for synthesis of the design. The design is coded using Very high speed integrated circuit Hardware Description Language (VHDL).