FPGA-Based High-Throughput and Scalable Matching Algorithm

Provided by: AICIT
Topic: Hardware
Format: PDF
In response to the need of a large number of regular expressions matching on high-speed network, in this paper, the authors present a FPGA-based hardware implementation, which can process multi-symbols per one clock cycle by using the Vector- and algorithm. Their approach was based on three basic modules to construct NFA that can be easily reused in a FPGA. This method can not only reduce the complexity of programming but also provide the basic of reconfigurable implementation. The approach proposed by the paper has good scalability that is tradeoff between throughput and the number of pattern symbols.

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