FPGA Based Implementation of 32 Bit RISC Processor

In this paper, a design of general purpose processor with a 5 stage pipeline, to incorporate programmable resources in to a processor. RISC processors have a CPI (clock per instruction) of one cycle. This is due to the optimization of each instruction on the CPU and a technique called pipelining. This technique allows each instruction to be processed in a set number of stages. This in turn allows for the simultaneous execution of a number of different instructions, each instruction being at a different stage in pipeline. The development approach of the overall system design depends on the design specification, analysis and simulation. The RISC Processor core is high performance 32-bit microprocessor. This processor make it especially suited to embedded control applications.

Provided by: International Journal of Engineering Research and Applications (IJERA) Topic: Data Centers Date Added: Jul 2011 Format: PDF

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