FPGA Based Implementation of Baseline JPEG Decoder

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Provided by: The International Journals of Engineering & Sciences (IJENS)
Topic: Hardware
Format: PDF
The JPEG standard (ISO/ IEC 10918-1 ITU-T recommendation T.81) defines compression techniques for image data. As a consequence, it allows to store and transfer image data with considerably reduced demand for storage space and bandwidth. From the four processes provided in the JPEG standard, only one, the baseline process is widely used. In this paper, FPGA based high speed, low complexity and low memory implementation of JPEG decoder is presented. The pipeline implementation of the system, allow decompressing multiple image blocks simultaneously.
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