FPGA-based implementation of UART
In this paper the authors focus on the hardware implementation of a high throughput Universal Asynchronous Receiver & Transmitter (UART) using FPGA. The UART described in this paper consist of the transmitter, the receiver and the baud rate generator. This has been implemented using verilog hardware description language and simulated using ModelSim SE 6.0d. The verilog description is synthesized on the Field Programmable Gate Array devices (FPGA) such as Virtex4 and Sparten3and a comparative study is done between the different characteristics.