In this paper, the authors present FPGA-based design of hybrid adder with the optimal bit-width configuration(out of a large number of possible configurations) of each of the sub-adders constitute the proposed hybrid adder using a high level automated methodology. Algebraic optimization model for the hybrid adder is built to produce the best choice of types and bit-widths of the sub-adders. In context of this paper, several classes of parallel adders are designed and its performance is evaluated to serve as sub-adders inside the hybrid adder.