FPGA Based Packet Classification Using Multi-Pipeline Architecture

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Provided by: Science Publishing Group
Topic: Hardware
Format: PDF
In this paper, the authors propose a decision-tree-based linear multi-pipeline architecture on FPGA's for packet sorting. They reflect on the next-generation packet classification problems where more than 5-tuple packet header fields have been classified. From traditional fixed 5-tuple matching, multi-field packet classification has been evolved for flexible matching with arbitrary combination of numerous packet header fields. The recently proposed open flow switching requires classifying each packet using up to 12-tuple packet header fields. It became a great task to develop scalable solutions for next-generation packet classification that support larger rule sets, additional packet header fields and higher throughput.
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