FPGA Fault Tolerant Arithmetic Logic: A Case Study Using Parallel-Prefix Adders

Provided by: Hindawi Publishing
Topic: Hardware
Format: PDF
In this paper, the authors examine fault tolerant adder designs implemented on FPGAs which are inspired by the methods of modular redundancy, roving, and gradual degradation. A parallel-prefix adder based upon the Kogge-Stone (KS) configuration is compared with the simple Ripple Carry Adder (RCA) design. The Kogge-Stone (KS) design utilizes a sparse carry tree complemented by several smaller RCAs. Additional RCAs are inserted into the design to allow fault tolerance to be achieved using the established methods of roving and gradual degradation. A Triple Modular Redundant Ripple Carry Adder (TMR-RCA) is used as a point of reference.

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