FPGA Implementation of (15, 7) BCH Encoder and Decoder for Audio Message

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Provided by: International Journal of Engineering Sciences & Research Technology (IJESRT)
Topic: Hardware
Format: PDF
In a communication channel, noise and interferences introduce the bit errors during the transmission of the digital message. To get the error free communication, error control codes are used. This paper discusses FPGA implementation of (15, 7) BCH encoder and decoder for audio message transmission and reception using Verilog hardware description language. Initially audio message is converted to digital data which are framed into binary data of 7 bits. These 7 bits are encoded into 15 bit code word using (15, 7) BCH encoder. If any 2 bit error occurs in any position of 15 bit code word, it is detected and corrected.
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