FPGA Implementation of 3 Bits BCH Error Correcting Codes

Provided by: International Journal of Computer Applications
Topic: Hardware
Format: PDF
In this paper, the authors describe the prototyping of a BCH code using a Field Programmable Gate Array (FPGA) reconfigurable chip. BCH code is one of the most important cyclic block codes. Designing on FPGA leads to a high calculation rate using parallelization (implementation is very fast) and it is easy to modify. BCH encoder and decoder have been designed and simulated using Matlab, Xilinx-ISE 10.1 web pack and implemented in a XC3S700A-4FG484 FPGA. In this paper, they used 15-bit size code word and 5-bits data, any 3-bits error in any position of 15-bits has been corrected.

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