FPGA Implementation of 32-Bit Wave-Pipelined Sparse-Tree Adder

Provided by: International Journal for Electrical, Electronics and Communication (IJEEC)
Topic: Hardware
Format: PDF
In this paper, the authors include the design, testing and architecture of the 32-bit asynchronous wave pipelined sparse-tree superconductor rapid single-flux quantum adder implemented. Compared to the Kogge Stone adder, the authors prefix parallel sparsetree adder has better efficiency on energy with significantly decreased complexity and almost no reduced operation frequency. The 32-bit adder core has 9941 Joseph-son junctions occupying an area of 8.5mm2. It is designed operation frequency targeted as 30 GHz with the expected latency of 352ps at bias voltage of2.5mV.

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