FPGA Implementation of 8-bit Multiplier with Reduced Delay Time

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Provided by: International Association of Computer Science & Information Technology (IACSIT)
Topic: Hardware
Format: PDF
In this paper the authors propose a design method for an 8-bit multiplication with reduced delay time. Normally, two numeric data can be multiplied by repeated addition. In case of binary multiplication, combinational circuit can be designed using manual multiplication method which requires binary addition. Carry generated because of addition affects the speed of multiplication since the present addition depends on the value of previous carry. To overcome this problem, addition with the help of multiplexer is introduced and the result is an increased speed in multiplication.
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