Fpga Implementation of 8-Bit Vedic Multiplier by Using Complex Numbers

Provided by: International Journal of Engineering Research and Applications (IJERA)
Topic: Hardware
Format: PDF
In this paper, the authors describe the implementation of 8-bit vedic multiplier using complex numbers previous technique describes that 8-bit vedic multiplier using barrel shifter by FPGA implementation comparing the both technique in this paper propagation delay is reduced so that processing of speed will be high 8-bit vedic multiplier using barrel shifter propagation delay nearly 22nsec but present technique 8-bit vedic multiplier using complex numbers where propagation delay is 19nsec. The design is implemented and verified by FPGA and ISE simulator.

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