FPGA Implementation of A Pipelined MIPS Soft Core Processor

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Provided by: International Journal of Innovative Research in Science, Engineering and Technology (IJIRSET)
Topic: Data Centers
Format: PDF
A soft-core processor is a model of Hardware Description Language (HDL) of a specific Central Processing Unit (CPU) that can be customized for a given application and synthesized for an ASIC or FPGA target. Usually they contain embedded processors that are often in the form of soft-core processors that execute software code. This paper presents a FPGA implementation & verification of a pipelined MIPS 32-bit (microprocessor without interlocked pipeline stages) processor. In this technique soft-core does not requires any reloading or reimplementation of processor after the modification of MIPS code.
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