International Journal of Emerging Technology and Advanced Engineering (IJETAE)
The high frequency resolution, short locking time and its spectral purity increases the popularity of phase locked loop in the major applications like wireless communications. This paper focuses on the FPGA implementation and analysis of All Digital Phase Locked Loop (ADPLL), as all the applications requires a cost effective low power and high speed phase locked loops. The design is validated through the Simulink software. This paper implements an ADPLL with Nyquist rate phase detector which is basically a digital multiplier, simulation results proves a very high speed of operation for low frequency ranges and resource utilization on FPGA proves the structure simpler.