International Journal of Advanced Technology in Engineering and Science (IJATES)
In this paper, the advanced encryption standard was implemented with pure hardware. However Field Programmable Gate Arrays (FPGAs) offer a more speed than existing implementations. This paper investigates the AES algorithm with regard to 256 bits message length and 192 bits key length. In Spartan3 EDK the authors implemented the AES algorithm through pipelined architecture through the soft core processor Micro Blaze which in deed used for developing a hardware structure which is configured using system C coding.