FPGA Implementation of an Efficient Vedic Multiplier
Multipliers are the most significant components in the design of many high performance FIR filters, image and digital signal processors in the upcoming digital world. Multipliers being the most area and power consuming elements of a design, area-efficient low-power multiplier architectures are in demand. In this paper, multiplier based on ancient Vedic mathematics technique has been proposed which employs full adders, compressors and other efficient components to achieve the desired parameters for the proposed design. Combining the Vedic Sutras-Urdhva Tiryagbhyam sutra and efficient compressors, a robust speed and area efficient multiplier architecture is achieved.