The wavelet transform has emerged as advanced technology in the field of VLSI implementation for image compression. Wavelet based coding provides improvements in picture quality at higher compression ratios. In this paper, the authors propose an efficient VLSI architecture for lifting based 5/3 DWT using FPGA. The lifting scheme 5/3 algorithm is used for implementing 1D-DWT architecture. The 2D-DWT lifting based architecture is designed using 1D-DWT lifting architectures. The proposed architecture uses less hardware interns of dedicated multipliers compared to existing architectures.