FPGA Implementation of Booth's and Baugh-Wooley Multiplier Using Verilog
In this paper, the authors have designed and implemented a Signed-Unsigned Booth's Multiplier and a Signed-Unsigned Baugh-Wooley Multiplier for 32-bits multiplication. The designing and verification is done through Verilog on Xilinx 12.4. In this paper, they tried to explain the step by step process that was adopted for Signed-Unsigned Booth's Multiplier. Also, two different approaches for implementing the Signed Baugh-Wooley multiplier in Singed-Unsigned Baugh-Wooley multiplier and after, the implementation they could see the differences in certain parameters. The array structure of Signed-Unsigned Booth's multiplier and Signed-Unsigned Baugh-Wooley multiplier is obtained from RTL synthesis are shown.