FPGA Implementation of Different Multiplier Architectures
Multiplication is one of the basic functions used in Digital Signal Processing (DSP). It requires more hardware resources and processing time than addition and subtraction. In fact, 8.72% of all instructions in a typical processing unit is multiplier. The multiplier is a fairly large block of a computing system. In this paper, 2 different multiplier architectures are implemented in xilink FPGA and compared for their performance. Here, these architectures are implemented for 4, 8, 16 bit. Based on various speed-up schemes for binary multiplication, a comprehensive overview of different multiplier architectures are given in this paper.