FPGA Implementation of Floating Point Reciprocator

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Provided by: Technicaljournalsonline
Topic: Hardware
Format: PDF
In this paper, an efficient FPGA implementation of a reciprocator for both IEEE single-precision and double-precision floating numbers is presented. This method is based on the use of Look-Up-Tables (LUTs) and partial block multipliers. Previously the LUTs and Multipliers are mostly used, in these methods accuracy is not achieved and area occupied by them is also more. In the proposed method, number of LUTs and multipliers are reduced such that performance in terms of frequency and accuracy is improved and also latency is reduced.
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