International Journal of Engineering and Advanced Technology (IJEAT)
In this paper, the authors have highlighted the concept of frame decoding behavior of flex ray communication protocol. The VHDL model of flex ray frame decoder of flex ray communication controller is designed. The design is simulated using ModelSim Altera edition 13.0 and synthesized using Quartus II 188.8.131.52. The frame decoding behavior is implemented using Stratix IV GX FPGA. This paper design is made with the intention of development of low power; high performance FPGA for decoding the data transmitted which will be a basic for the development of flex ray communication controller.