FPGA Implementation of High Speed FIR Filter Using Carry Select Adder in VHDL

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Provided by: Creative Commons
Topic: Hardware
Format: PDF
In today's world, the most widely used operation in digital signal processing is the FIR filtering operation. With increasing complexity of the digital circuit's efficient performance is one of the main parameter to be considered while designing an FIR filter and this is the main reason for the popularity of the DSP systems. Efficient performance and area of the system are the two basic parameters which are inversely related to each other. With increase in the time efficiency of the FIR filter the area can be optimized accordingly.
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